The present disclosure relates generally to data storage systems, and more specifically, but not by limitation, to a data memory and controlling device having interface error detection and handling logic.
Many data memory devices support interfaces through which commands and data are sent from a controller device. The memory device performs an operation based upon the command sent. For example, most NAND flash data memory devices support a variety of commands related to the storage of data within the device. Over an interface, data can be erased, programmed, read, and/or copied by sending various commands to the NAND flash from a controlling device (e.g., a flash controller). Unfortunately, the commands, data, parameters, and/or status information, for example, associated with these operations can contain errors.
The discussion above is merely provided for general background information and is not intended to be used as an aid in determining the scope of the claimed subject matter.